In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals produced by an IC tester at its appropriate tester pins (channels) at predetermined test timings. The IC tester receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed by strobe signals with predetermined timings to be compared with expected data to determine whether or not the IC device properly performs the intended functions. This is a basic process for testing a logic device by a semiconductor test system.
A semiconductor device to be tested may also include analog functional blocks such as an AD converter and/or a DA converter as well as a digital functional block. Such a semiconductor device is sometimes called a mixed signal IC. An example of such a mixed signal IC is a semiconductor integrated circuit designed for modems, audio and/or video devices, and the like.
An example of semiconductor test system for testing such a mixed signal IC device (mixed signal test system) in the conventional technology is shown in FIGS. 4-7. FIG. 4 shows a basic structure in the conventional mixed signal test system and FIGS. 5-7 relate to a digitizer in the mixed signal test system. A device under test (DUT) is a mixed signal IC including an analog function and a digital function. When testing, the DUT is place on a test station to receive test signals from the mixed signal test system and produce response outputs. The mixed signal test system of FIG. 4 includes a functional test unit (FTU) for testing a digital function of the DUT and an analog test unit (ATU) for testing an analog function of the DUT and a synchronous control unit 40 for synchronizing the functional test unit (FTU) and the analog test unit (ATU) with one another.
In FIGS. 4 and 5, the functional test unit (FTU) includes a timing generator TG, a pattern generator such as an algorithmic pattern generator (ALPG) or a sequential pattern generator (SQPG), and a format controller (FC). The functional test unit (FTU) has a large number of tester pins (channels), such as 256 pins, corresponding to terminal pins of the device to be tested (DUT) . At the output of the format controller FC, each tester pin provides a test pattern to the corresponding pin of the DUT.
The timing generator TG generates timing signals such as a rate clock to synchronize the timing of the functional test unit and provides the timing pulses to the pattern generator SQPG. The test pattern generator SQPG generates a test pattern based on a test program in response to the rate clock from the timing generator TG. The timing generator TG also generates timing data and wave form data to be used in the format controller FC to produce tester rates, delay timings and wave forms in the test pattern. The test pattern at the output of the format controller FC is provided to the DUT through a pin electronics PE.
The synchronous control unit 40, although not shown, includes an event master and a digital/analog synchronous controller. In receiving signals generated by the pattern generator SQPG, the synchronous control unit 40 produces a start signal and a trigger signal to be provided to the analog test unit (ATU). The start signal and trigger signal are used to synchronize test patterns generated by the functional test unit FTU and test signals generated by the analog test unit and measurement timings in the analog test unit. A clock generator 48 receives clock signals such as the rate clock from the timing generator TG and a clock from a synthesized signal generator (SSG) in the analog test unit to produce appropriate clock signals to be used in the analog test unit (ATU).
In the example of FIG. 4, the analog test unit (ATU) includes a variety of functional blocks such as a digital arbitrary wave form generator (DAW) for generating digital wave form data, an acquisition memory (AQM) for storing digital codes of an output signal of the DUT, a synthesized signal generator (SSG) for generating signals of various frequencies, an arbitrary wave form generator (AWG) for generating signals with wave forms defined by the wave form data from DAW, a digitizer (DGT) for converting an analog signal into a digital signal, a time measurement unit (TMU) for measuring time intervals and frequencies of an incoming signal, a precision voltage generator (PVS) for generating a reference DC voltage, a precision voltage meter (PVM) for measuring a DC voltage, a digital signal processor (DSP) for digital processing on digital data and a controller (CPU) for an overall operational control of the analog test unit(ATU).
Plural sets of the above listed resources may be provided in the analog test unit for performing signal generation and signal measurements in response to the synchronous signal from the synchronous control unit 40. The analog test unit and the terminal pins of the DUT are connected through the pin electronics (PE).
FIG. 5 schematically shows a structure in the digitizer (DGT) in the analog test unit (ATU). The digitizer DGT of FIG. 5 includes a filter (FLT) 60 and an AD converter (ADC) 30. Since a wide variety of output signals, such as high speed signals or high precision wave forms, will be produced by the DUT, the AD converter 30 may constitute a plurality of AD converters with different degrees of speed and resolution. For example, the AD converter may include a combination of a high speed AD converter with 12-bit resolution and 100 MHz sampling rate and a high precision AD converter with 26-bit resolution and 100 KHz sampling rate.
The filter 60 is an antialiasing filter which is typically a low pass filter to prevent aliasing effects involved in a sampling process. A plurality of such filters with different pass band frequencies may be selectively used depending on the sampling frequencies. Typically, as an antialiasing filter, the filter 30 removes frequency components higher than ½ of the sampling frequency fc from the output signal of the DUT received through the pin electronics PE. The output of the filter 60 is provided to the AD converter 30.
The AD converter 30 samples an input signal from the filter 60 at each edge of the sampling clock 40clk having a sampling frequency fc and converts the sampled voltage to a digital signal, i.e., code data 30s. The code data 30s is stored in the acquisition memory (AQM) 50 in response to a memory timing signal 47s from the synchronous control unit 40. The stored data in the acquisition memory (AQM) 50 is used for signal analysis and evaluation such as by the digital signal processor (DSP) 64.
Since high resolution data can be obtained by increasing the number of sampling points, generally, a digitizer uses a highest possible sampling frequency to achieve both high even higher than the highest sampling frequency of an AD converter, an example of circuit arrangement such as shown is FIG. 6 is used in the conventional technology. In FIG. 6, two AD converters 31 and 32 are arranged so as to operate in an interleave fashion for increasing the overall sampling speed by two times of each AD converter.
Namely, the digitizer of FIG. 6 includes a filter (FLT) 60, a first AD converter 31, a second AD converter 32, and a multiplexer 35. The filter 60 is designed to function as an antialiasing filter for an equivalent sampling frequency fce which is two times higher than a sampling frequency of each of the AD converters 31 and 32. The synchronous control unit 40 provides sampling clocks 41clk and 42clk to the first and second AD converters 31 and 32, respectively. The synchronous control unit 40 also provides a square wave clock 45s to the multiplexer 35, and a memory timing signal 47s to the acquisition memory 50.
FIGS. 7A-7C are timing charts showing the timing relationship between the first and second AD converters 31 and 32 and an overall sampling rate at the output of the multiplexer 35. As shown in FIG. 7A, the first AD converter 31 samples an input signal Si from the filter 60 by a first sampling clock 41clk from the synchronous control unit 40 which is the highest possible sampling frequency. As shown in FIG. 7B, the second AD converter 32 samples the input signal Si from the filter 60 by a second sampling clock 42clk from the synchronous control unit 40 which is the highest possible sampling frequency.
The multiplexer 35 receives the digitized codes from the first and second AD converters 31 and 32 and alternately selects the codes at the timing of each rising edge and falling edge of the square clock signal 45s having the same repetition rate as that of the sampling clocks 41clk and 42clk. The clock signal 45s has a square shape so as to have the same time interval between any adjoining two edges. Thus, an output signal 35s of the multiplexer 35 has an equivalent sampling frequency fce which is two times higher than the clock rate of the first or second sampling clock.
In the example of FIGS. 6 and 7, although only two AD converters are shown just for an illustration purpose, three or more AD converters are used to establish three or more higher equivalent sampling rates. Namely, in the conventional technology, to increase the overall sampling rate, a plurality of AD converters are arranged to operate in parallel fashion while the outputs of the AD converters are combined to form a serial signal having a repetition rate which is the plurality of times higher than that of each AD converter.
In the conventional technology, however, to increase the overall sampling rate, the number of circuit components such as AD converters increases in proportion to the increase of the sampling rate. As a consequence, in the conventional technology involving the interleave method, there is a problem that the circuit size and cost of the digitizer increases with the increase of the sampling rate.